By isolating different software tasks, the architecture ensures that a vulnerability in a web-facing application cannot lead to a compromise of the core system kernel. Cryptographic Acceleration
External Memory Map: Defines protected regions in DDR or Flash memory. 🚀 Key Features and Capabilities
Be prepared to sign a Non-Disclosure Agreement if your company does not already have one in place with NXP. NXP Community Core Features of Trust Architecture 2.1 qoriq trust architecture 21 user guide
to create a formal request for the "QorIQ Trust Architecture 2.1 User Guide". Sign an NDA:
For ARM-based QorIQ LS-series, the guide ties QorIQ’s security monitor (SEC-MON) with ARM TrustZone. It details how to partition memory, configure TrustZone address space controllers (TZASC), and handle secure interrupts. This is rare in vendor documentation – most treat TrustZone separately. NXP Community Core Features of Trust Architecture 2
This document is published by NXP Semiconductors. You can find the official PDF by searching for the document number or title on the NXP website.
When the Normal World (Linux) needs to encrypt a packet, it cannot touch the key directly. Instead, it issues a "Secure Monitor Call" (SMC). The processor context-switches into the Secure World, performs the encryption using the hidden key, and returns only the ciphertext to the Normal World. It details how to partition memory, configure TrustZone
The “Trust Architecture 1.1” name suggests a general framework, but much of the guide is ARM-specific (TrustZone). Users of PowerPC-based QorIQ (P-series) will find irrelevant sections. Also, references to older Code Signing Tool (CST) versions (e.g., v2.0) conflict with newer CST v3.x commands, leading to confusion.